CCD comprises a channel region (charge transfer channel region) formed on a surface of a semiconductor substrate, and a plurality of transfer electrodes arranged in the channel region along a direction of charge transfer. Adjacent transfer electrodes are formed by using, for example, two layers of polysilicon to enable boundaries thereof to overlap each other whereby a fringe electric field is preferably generated below the boundaries of the transfer electrodes and an improvement in charge transfer efficiency is achieved.
An explanation is given to the prior art by taking up a horizontal shift register of a CCD image sensor as an example of a conventional CCD. FIG. 1 is a schematic plan view showing the structure, on an output end side, of a horizontal shift register of a conventional CCD image sensor. The horizontal shift register is driven at two-phase transfer clocks φ1, φ2, and two aluminum (Al) wirings 4, 6 arranged along a channel region 2 supply the transfer clocks φ1, φ2 to transfer electrodes.
Electrodes formed from a first layer polysilicon (referred below to as 1st poly-Si) and electrodes formed from a second layer polysilicon (referred below to as 2nd poly-Si) are arranged as transfer electrodes alternately along the channel region 2, and the two adjacent transfer electrodes are paired to correspond to one transfer clock. 2nd poly-Si electrodes 8 formed after formation of 1st poly-Si electrodes 10 are caused to overlap respective edges of the 1st poly-Si electrodes 10 on both ends thereof so that misalignment in lithography generates no gap between the 2nd poly-Si electrodes and adjacent 1st poly-Si electrodes 10.
The horizontal shift register comprises a main portion 12 and an extension 14. The main portion 12 receives signal charges transferred vertically from an imaging portion. The extension 14 is connected to an end of the main portion 12 and is gradually narrowed in channel width. An output end of the extension 14 is connected to an output portion 16.
The output portion 16 comprises a floating diffusion (FD) 18, of which electric potential is varied according to a quantity of signal charge transferred from the horizontal shift register. An output gate electrode (OG) 20 is arranged between the last-stage transfer electrode 10, to which transfer clock of the horizontal shift register is applied, and the FD 18. The OG 20 is made of polysilicon and formed into an elongate shape extending alongside of the transfer electrode 10 to be connected to an Al wiring 22. Here, the OG 20 is made of 2nd poly-Si so as to restrict a gap between it and an adjacent transfer electrode 10 made of 1st poly-Si, and structured so that an edge thereof on a side of the last-stage transfer electrode 10 overlaps the transfer electrode 10. The OG 20 is applied by a certain electric potential to maintain channel electric potential therebelow constant. The channel electric potential is set to be shallower than reset electric potential of the FD 18, and a maximum quantity of signal charge being able to be stored in the FD 18 is determined according to a difference between channel electric potential below the OG 20 and reset electric potential of the FD 18.
The transfer electrodes of the CCD shift register such as the electrodes 8, 10 and the OG 20 are extended even outside the channel region. In particular, a distance between the channel region and the wirings, through which voltage is applied to the transfer electrodes, is liable to be increased in that portion of the channel region, which is narrowed in channel width, and lengths, by which the transfer electrodes are extended outside the channel region, are correspondingly increased. With a conventional structure, adjacent transfer electrodes overlap each other also outside a channel region and capacity between the transfer electrodes is increased correspondingly. Therefore, the problem caused is that when transfer clock is applied to a certain transfer electrode, even a channel electric potential below adjacent transfer electrodes is dragged to vary. The problem specifically appears as inconveniences such as deterioration of a CCD shift register in transfer efficiency, reduction in charge handling capacity, and noise increase.
In particular, overlap of that last-stage transfer electrode, to which transfer clock is applied, and an OG causes variation in channel electric potential below the OG according to the transfer clock and can cause variation in maximum quantity of signal charge being able to be stored in a FD, and variation in capacitance of the FD. Consequently, the problem caused is that noise is liable to be generated in output signal taken out by means of the FD on the basis of the quantity of signal charge.